1. Field of the Invention
The present invention relates a multiplier and more particularly, to a multiplier for analog signals using quadritail cells or circuits formed of bipolar transistors or metal-oxide-semiconductor (MOS) transistors, which is formed on semiconductor integrated circuits.
2. Description of the Prior Art
It is well known that an analog multiplier is composed of an adder 1, a first subtracter 2, a first squarer 3, a second squarer 4 and a second subtracter 5, as shown in FIG. 1. In FIG. 1, a first analog input signal (voltage V.sub.1) and a second analog input signal (voltage V.sub.2) are respectively applied in parallel to the adder 1 and the first subtracter 2. The adder 1 outputs a voltage (V.sub.1 +V.sub.2) which is the sum of the first and second input voltages V.sub.1 and V.sub.2, the first subtracter 2 outputs a voltage (V.sub.1 -V.sub.2) which is the difference thereof. The output of the adder 1 is squared in the first squarer 3 and the output of the subtracter 2 is squared in the second square 4, and then the outputs of the first and second squarer 3 and 4 are sent to the second subtracter 5. In the second subtracter 5, since an operation such as (V.sub.1 +V.sub.2).sup.2 -(V.sub.1 -V.sub.2).sup.2 is carried out, an output voltage V.sub.0 of 4V.sub.1 V.sub.2 can be obtained. This means that the circuit shown in FIG. 1 has a function of multiplying the first and second input signals.
The inventor has developed a squarer composed of two differential pair each of which has two MOS transistors different in capacity from each other. Here, the "capacity" of the MOS transistor means that a ratio of the gate width W to the gate length L, or (W/L). Besides, the inventor has filed a Japanese patent application about a multiplier as shown in FIG. 2, in which the inventor's squarer is used as the first and second squarers 2 and 3 respectively and the adder 1 and the first subtracter 2 are respectively composed of differential pairs of MOS transistors (see Japanese Non-Examined Patent Publication 3-210683 and its correslonding U.S. Pat. No. 5,107,150).
The prior art multiplier shown in FIG. 2 is composed of MOS transistors. An adder 6 is comprised of four MOS transistors M51, M52, M53 and M54 whose capacities are the same, and two constant current sources (current I.sub.0) which drive the pair of the transistors M51 and M52 and that of the transistors M53 and M54, respectively. The first input voltage V.sub.1 is applied between the input ends or gates of the transistors M51 and M52. The second input voltage V.sub.2 is applied between the input ends or gates of the transistors M53 and M54.
A first subtracter 7 has a similar configuration to the adder 6, however, is different therefrom in input voltage. The subtracter 7 is comprised of four MOS transistors M59, M60, M61 and M62 whose capacities (W/L) are the same, and two constant current sources (current I.sub.0) which drive the pair of the transistors M59 and M60 and that of the transistors M61 and M62, respectively. The first input voltage V.sub.1 is applied between the input ends or gates of the transistors M59 and M60 with the same polarity as that of the transistors M51 and M52 of the adder 6. The second input voltage V.sub.2 is applied between the input ends or gates of the transistors M61 and M62 with the opposite polarity as that of the transistors M53 and M54 of the adder 6.
The first squarer 8 is comprised of four MOS transistors M55, M56, M57 and M58 and two constant current sources (current I.sub.01) which drive the pair of the transistors M55 and M56 and that of the transistors M57 and M58, respectively. The transistors M55 and M56 are different in capacity from each other and the transistors M57 and M58 are also different in capacity from each other. When the capacities of the transistors M55, M56, M57 and M58 are defined as (W55/L55), (W56/L56), (W57/L57) and (W58/L58), respectively, EQU (W56/L56)/(W55/L55)=(W58/L58)/(W57/L57)=K
is established, where K&gt;1.
The gates of the transistors M55 and M58 are connected to the drains of the transistors M52 and M54, the gates of the transistors M56 and M57 are connected to the drains of the transistors M51 and M53.
The second squarer 9 has a similar configuration to that of the first squarer 8. The second squarer 9 is comprised of four MOS transistors M63, M64, M65 and M66 and two constant current sources (current I.sub.01) which drive the pair of the transistors M63 and M64 and that of the transistors M65 and M66, respectively. The transistors M63 and M64 are different in capacity from each other and the transistors M65 and M66 are also different in capacity from each other. Similar to the first squarer 8, the capacities (W63/L63), (W64/L64), (W65/L65) and (W66/L66) of the respective transistors M63, M64, M65 and M66 has the following relationships as EQU (W64/L64)/(W63/L63)=(W66/L66)/(W65/L65)=K
where K&gt;1.
In the second squarer 9, the gates of the transistors M63 and M66 are connected to the drains of the transistors M60 and M62 of the first subtracter 7, and the gates of the transistors M64 and M65 are connected to the drains of the transistors M63 and M65 thereof. Further, the gates of the transistors M64 and M65 are connected to the drains of the transistors M59 and M61 of the first subtracter 7, on the one hand, and connected to the drains of the transistors M56 and M58 of the first squarer 8, on the other hand.
The drains of the transistors M55 and M57 of the first squarer 8 and the drains of the transistors M66 and M64 of the second squarer 9 are connected in common to form one of output ends. The drains of the transistors M56 and M58 of the first squarer 8 and the drains of the transistors M65 and M63 of the second squarer 9 are connected in common to form the other of the output ends. These output ends thus formed are respectively connected to the input ends of the second subtracter 10.
Next, the operation principle of the prior art multiplier as above will be described below.
With the adder 6, since the four MOS transistors M51, M52, M53 and M54 are equal in capacity (W/L) to each other, they have the same transconductance parameters, respectively. Then, the transconductance parameter .alpha..sub.1 is expressed as EQU .alpha..sub.1 =(1/2).mu..sub.n C.sub.0X (W51/L51)
using the capacity (W51/L51) of the transistor M51, where .mu..sub.n is the carrier mobility, C.sub.0X is the gate oxide capacitance per unit area, so that the drain currents I.sub.d1, I.sub.d2, I.sub.d3 and I.sub.d4 of the respective transistors M51, M52, M53 and M54 are expressed as the following equations 1--1, 1-2, 1-3 and 1-4, respectively, where V.sub.GS1, V.sub.GS2, V.sub.GS3 and V.sub.GS4 are the gate-source voltages of the transistors M51, M52, M53 and M54, respectively, and V.sub.TH is the threshold voltage of these transistors. EQU I.sub.d1 =.alpha..sub.1 (V.sub.GS1 -V.sub.TH).sup.2 ( 1--1) EQU I.sub.d2 =.alpha..sub.1 (V.sub.GS2 -V.sub.TH).sup.2 ( 1--2) EQU I.sub.d3 =.alpha..sub.1 (V.sub.GS3 -V.sub.TH).sup.2 ( 1-3) EQU I.sub.d4 =.alpha..sub.1 (V.sub.GS4 -V.sub.TH).sup.2 ( 1-4)
Besides, I.sub.d1 +I.sub.d2 =I.sub.0, I.sub.d3 +I.sub.d4 =I.sub.0, V.sub.GS1 -V.sub.GS2 =V.sub.1, V.sub.GS3 -V.sub.GS4 =V.sub.2 are established, and the current differences (I.sub.d1 -I.sub.d2) and (I.sub.d3 -I.sub.d4) are expressed as the following equations 2 and 3, respectively, so that the differential output current (I.sub.A -I.sub.B) can be obtained as the following equation 4. ##EQU1##
The equations 2 and 3 show the transfer characteristics of the differential pair of the MOS transistors. From the equations 2 and 3, it is seen that the current differences (I.sub.d1 -I.sub.d2) and (I.sub.d3 -I.sub.d4) are in proportion to the input voltages V.sub.1 and V.sub.2 in small signal applications, respectively. Therefore, from the equation 4, the differential output current (I.sub.A -I.sub.B) has an adding characteristic with good linearity when the input voltages V.sub.1 and V.sub.2 are small in value.
In order to use the adder 6 as a subtracter, the second input voltage V.sub.2 is required to be applied thereto with opposite polarity. Then, in the first subtracter 7, the second input voltage V.sub.2 is applied thereto with such polarity.
With the first subtracter 7, the drain currents of the respective transistors M59, M60, M61 and M62 are defined as I.sub.d11, I.sub.d12, I.sub.d13 and I.sub.d14, respectively, the current differences (I.sub.d11 -I.sub.d12) and (I.sub.d13 -I.sub.d14) are expressed as the following equations 5 and 6, respectively, and the differential output current (I.sub.c -I.sub.D) is expressed as the following equation 7. ##EQU2##
Accordingly, the differential output voltage V.sub.A of the adder 6 and the differential output voltage V.sub.B of the first subtracter 7 are expressed as the following equations 8 and 9, respectively. ##EQU3##
With the first squarer 8, since the capacity ratios (W56/L56)/(W55/L55) and (W58/L58)/(W57/L57) of the MOS transistors M55 and M56 and the transistors M57 and M58 are K. The transconductance parameter .alpha..sub.2 is expressed as EQU .alpha..sub.2 =(1/2).mu..sub.n C.sub.OX (W55/L55)
using the capacity (W55/L55) of the transistor M55, so that the drain currents I.sub.d5, I.sub.d6, I.sub.d7 and I.sub.d8 of the respective transistors M55, M56, M57 and M58 are expressed as the following equations 10-1, 10-2, 10-3 and 10-4, respectively, where V.sub.GS5, V.sub.GS6, V.sub.GS7 and V.sub.GS8 are the gate-source voltages of the transistors M55, M56, M57 and M58, respectively, and V.sub.TH is the threshold voltage of these transistors. EQU I.sub.d5 =.alpha..sub.2 (V.sub.GS5 -V.sub.TH).sup.2 ( 10-1) EQU I.sub.d6 =k.alpha..sub.2 (V.sub.GS6 -V.sub.TH).sup.2 ( 10-2) EQU I.sub.d7 .alpha..sub.2 (V.sub.GS7 -V.sub.TH).sup.2 ( 10-3) EQU I.sub.d8 =k .alpha..sub.2 (V.sub.GS8 -V.sub.1H).sup.2 ( 10-4)
Besides, I.sub.d5 +I.sub.d6 =I.sub.01, I.sub.d7 +I.sub.d8 =I.sub.01, V.sub.GS5 -V.sub.GS6 =V.sub.GS8 -V.sub.GS7 =V.sub.A are established, and the current differences (I.sub.d5 -I.sub.d6) and (I.sub.d7 -I.sub.d8) are expressed as the following equations 11 and 12, respectively. ##EQU4##
Then, the differential output current (I.sub.E -I.sub.F) can be expressed as the following equation 13. From the equation 13, it is seen that the differential output current (I.sub.E -I.sub.F) is in proportion to the square of the input voltage V.sub.A. ##EQU5##
With the second squarer 9, the differential output current (I.sub.G -I.sub.H) can be expressed as the following equation 14, in the same way, where I.sub.d15, I.sub.d16, I.sub.d17 and I.sub.d18 are the drain currents of the respective transistors M63, M64, M65 and M66. From the equation 14, it is seen that the differential output current (I.sub.G -I.sub.H) is in proportion to the square of its input voltage V.sub.B. ##EQU6##
In the second subtracter 10, the differential output currents I.sub.z (=I.sub.E -I.sub.F) and I.sub.2 (=I.sub.G -I.sub.H) of the first and second squarers 9 and 10 are added with their polarity being opposite, so that the differential current (I.sub.1 -I.sub.2) is expressed as the following equation 15. ##EQU7##
By substituting the equations 8 and 9 into the equation 15 to replace V.sub.A and V.sub.B, the following equation 16 can be obtained. ##EQU8##
Then, by ignoring the terms of V.sub.1.sup.2 and V.sub.2.sup.2 in the equation 16, the following equation 17 can be given. From the equation 17, it is seen that the circuit shown in FIG. 2 has a multiplying function. ##EQU9##
FIG. 3 shows a result of computer simulation, which is carried out under the condition that R.sub.L =5 k.OMEGA., I.sub.0 =100 .mu.A, I.sub.01 = 10 .mu.A, W51=20 .mu.m, L51=5 .mu.m, W55=10 .mu.m, L55=5 .mu.m, K=5, C.sub.0X =320 .ANG..
FIG. 3 shows the relations between the differential output current and the first input voltage V.sub.1 with the second input voltage V.sub.2 as a parameter, however, the same result is obtained by replacing the first input voltage V.sub.1 with the second input voltage V.sub.2, and vice versa.
The prior art multiplier shown in FIG. 2 is comprised of MOS transistors, however, the same multiplying operation can be obtained by using bipolar transistors in place of the MOS transistors. In the case, each squarer is composed of a differential pair of transistors whose emitter area are different from each other.
It is well known that there is the minimum unit (area) of a transistor formed on semiconductor integrated circuits in order to generate desired functions, so that it is preferable to form all transistors as the minimum unit considering its current consumption. However, with the prior art multiplier shown in FIG. 2, since each differential pair of the first and second squarers is comprised of two MOS transistors whose capacities or (W/L) are different each other, all the transistors cannot be formed as the minimum unit, and as a result, there arises a problem that current consumption of the integrated circuits is made large.
In addition, with the prior art multiplier, each differential pair is provided with a constant current source, so that four constant current sources are required in total for the first and second squarers. As a result, there arises another problem that the configuration of the integrated circuits is complex.